The present invention relates to a semiconductor storage device and a method for controlling the semiconductor storage device, and more particularly, to a semiconductor storage device having a verify function and a method for controlling the semiconductor storage device.
In recent years, many flash memories have been used as nonvolatile semiconductor storage devices. Such a flash memory performs verify processing to determine the correctness of a write operation and an erase operation. For example, in write verify processing, write data to a memory cell is an expectation value, read data obtained by reading data written in the memory cell is compared with the expectation value, and the correctness of the write operation is determined by the match or mismatch between the write data and the read data.
Japanese Unexamined Patent Publication No. 2004-318941 (Patent Document 1) discloses a technique related to a semiconductor storage device having a hierarchical bit line structure. In the semiconductor storage device disclosed in Patent Document 1, a memory array is divided, and bit lines have a hierarchical structure, thus making it possible to reduce the input load capacitance of a sense amplifier. Therefore, it is possible to enhance the reading speed of the semiconductor storage device.